The present invention relates to a semiconductor memory and its fabrication method, particularly to a self-amplifying memory cell which is a large-scale dynamic random access memory (hereafter referred to as a DRAM), allowing ultra-high integration density, and which has two field effect transistors and requires no charge storage capacitor.
DRAMs have been improved in integration degree up to four times in three years, and mass production of 4-megabit DRAMs is being started. This high integration has been achieved by greatly decreasing the element dimensions.
An existing DRAM, as shown by an equivalent circuit diagram in FIG. 6, comprises at least a storage capacitor 101 for storing charges, a bit line (DL) for feeding charges to the capacitor, a switching transistor (SM) for controlling the flow of charges, and a word line (WL) connected to the gate of the switching transistor.
In the structure of the existing DRAM memory cell (because the cell is a one-transistor-one-capacitor cell, it is hereafter referred to as a 1T-1C cell), it is a large problem to maintain reliability because troubles such as decrease of signal-to-noise ratio (hereafter referred to as SN ratio) and data inversion due to incoming alpha rays occur since the number of stored charges is decreased due to a great reduction of the cell area and decrease of the supply voltage.
Therefore, a so-called stacked type cell, made by forming part of a storage capacitor on a switching transistor or on an element-isolation oxide film, and a trenched cell made by forming a deep trench in a substrate and a charge storage capacitor on the side wall of the trench, are main cell structures used, after 4-megabit DRAMs, as a memory cell capable of increasing the number of stored charges even if the cell area is greatly decreased.
Trial fabrication of 16- and 64-megabit DRAM cells has been attempted by making full use of the above three-dimensional cell and a self-alignment process. However, if the memory cell area is decreased according to the existing trend, the cell area comes to approximately 0.5 .mu.m.sup.2 in 256-megabit DRAMs. To realize a large-enough storage capacitor in the very small cell area, it is necessary to use a very thin capacitor insulating film for the stacked type cell, or to form a deep trench with a depth of 5 .mu.m, an opening width of approximately 0.3 .mu.m, and an aspect ratio of 15 or more for the trenched cell. However, it is very difficult to solve these problems with existing semiconductor processing techniques.
Instead, various so-called self-amplifying memory cell structures have been proposed which do not require a relatively-large charge storage capacitor, by substituting for the charge storage capacitor an active transistor.
FIG. 7 is an equivalent circuit diagram of a self-amplifying memory cell comprising two n-channel field effect transistors (WM and RM), two bit lines (WD and RD), and two word lines (WW and RW), proposed in Extended Abstract of 16th Conference on Solid State Device and Materials, Kobe, 1984, pp. 265-268. The self-amplifying memory cell in FIG. 7 has a reading transistor (RM) having a floating gate which acts as a charge storage node, instead of the existing charge storage capacitor. To write data in the cell, a certain potential is applied to the writing word line (WW) and reading word line (RW) before applying "ground potential" or "positive potential" to the writing bit line (WD), in accordance with "0" or "1" of stored data, to control the number of positive charges of the charge storage node. The threshold voltage (Vth) of the reading transistor (RM) is decreased in accordance with the number of positive charges of the charge storage node and turned on. After data is written, the wiring word line (WW) is fixed to the ground potential.
To read stored data, a certain potential is applied to the reading word line (RW) to detect the potential fluctuation of the reading bit line (RD) caused by the "on" or "off" state of the reading transistor (RM). In this case, the drain electrode potential Vss of the reading transistor (RM) is fixed to the supply voltage. This cell can be operated even if the node capacitance ratio between the storage node and the reading-transistor channel is relatively small. However, the cell area cannot greatly be decreased because the cell requires lines twice as many as those of the existing memory cell (that is, 2 word lines and 2 data lines).
Unlike the above cell, Japanese Patent Laid-Open No. 5269/1985 discloses a cell comprising one bit line (DL) and two word lines (WW and RW), as shown by an equivalent circuit in FIG. 8(a).
To write data in this cell, the reading word line (RW) is grounded and a certain voltage is applied to the writing word line (WW). Under the above state, the potential of the bit line (DL) is transmitted to the floating gate of the reading transistor (RM), serving as the charge storage node, through the writing transistor (WM), to store positive or negative charges in or to draw them from the floating gate and write the data of "0" or "1" by grounding or raising the potential of the bit line (DL).
To read data from this cell, the writing word line (WW) is grounded and a certain potential is applied to the reading word line (RW). In this case, the reading transistor (RM) is turned off unless charges are stored in the charge storage node, and turned on if charges are stored in it. Therefore, the potential of the bit line (DL) changes according to "0" or "1" of stored data, and data can be read. In this case, the potential Vss of the drain electrode of the reading transistor (RM) is fixed to the ground potential or supply voltage. Also in this cell, it is difficult to greatly decrease the cell area because two word lines are arranged.
This Japanese Patent Laid-Open No. 25269/1985 discloses a cell comprising one bit line (DL) and one word line (WL), in a memory cell having a writing transistor (WM), and a reading transistor (RM) having a floating gate. See FIG. 8(b). In this embodiment shown herein in FIG. 8(b), both the writing transistor and the reading transistor are of the same conductivity type. Moreover, during operation of the memory cell the standby potential (Vw(S)) applied to the word line is less than the potential applied to the word line both during writing (Vw(W)) and during reading (Vw(R)). See FIG. 8(c).
The structure, and operation thereof, shown in FIG. 8(b) and 8(c) herein, have the following deficiencies. The potential applied to the word line during reading is dependent not only on the threshold voltage of the reading transistor (Vth(RM)), but is also dependent on the change in threshold voltage (Vth) shown in FIG. 8(c). Moreover, the threshold voltage of the writing transistor should be within the range of this change in threshold voltage shown in FIG. 8(c). In addition, this change in threshold voltage is relatively large--greater than 0.8-1.0 V.
Because all of the existing self-amplifying memory cells detect potential with the source-drain current of the reading transistor, they essentially perform nondestructive reading unlike the existing 1T-1C cells. Therefore, it is possible to basically decrease the number of stored charges. However, since stored charges are extinguished by the leak current of the writing transistor, refreshing is necessary similarly to the existing cell.
In the existing 1T-1C cell, word and data lines are arranged at minimum dimensions. Therefore, the cell area of the normal folded bit-line cell arrangement equals the value (word line pitch.times.2).times.(data line pitch). However, the above-mentioned existing self-amplifying memory cell requires a number of metal layers 1.5 to 2 times as much as the 1T-1C cell constitution. Therefore, the memory cell has a critical problem for high integration of DRAMs that the cell area increases three to four times.
Another problem is that it is difficult to secure a stable operation of the self-amplifying memory cell, in particular, sufficient data holding time. For example, to stably operate a 256-megabit DRAM, it is necessary to decrease the leak current per cell to 10.sup.-15 A or less. For the cells in FIGS. 7 and 8(a), however, it is inevitable to form either of the writing transistor (WM) and reading transistor (RM) in a polycrystalline silicon thin film. Therefore, because leak current passing through the grain boundary of the polycrystalline silicon thin film increases, it is very difficult to decrease the leak current per cell to 10.sup.-12 A or less. This is a critical defect for a DRAM.
Moreover, because the source-drain region of either of the writing transistor (WM) and reading transistor (WM) are formed in a polycrystalline silicon thin film having a large impurity diffusion coefficient compared with a single crystal, it is difficult to increase and control the channel length.
As described above, it is difficult to stably operate the existing self-amplifying memory cell and decrease the cell area because of various factors and it is not effective to decrease the cell area by substituting a capacitor with a transistor.